The Low Level Hardware Description language is an intermediate representation for digital circuit descriptions, together with an accompanying simulator and SystemVerilog/VHDL compiler.
LLHD separates input languages from EDA tools such as simulators, synthesizers, and placers/routers. This makes writing such tools easier, allows for more rich and complex HDLs, and does not require vendors to agree upon the implementation of a language.
Project components:
Edit the SystemVerilog on the left and see how it translates to LLHD on the right.
The scientific paper on LLHD is available on arXiv:
Are you interested in using open-source ideas to re-invent the hardware design software stack? Do you see LLHD as step one of a bigger picture and dream about extending it with formal verification, hardware synthesis, etc.? We are continuously looking for future PhD students and postdocs who are excited to work in this direction. For more details check out grosser.science or just write an informal email to tobias@grosser.es for us to discuss potential next steps.